 PARAMNet-II,
a low latency, high bandwidth interconnect, provides data
rates of 2.5 Gigabits/sec in full duplex over fiber. The
message latency is as low as 10 µsec.
PARAMNet-II uses a 16 port switch
and a Network Interface Card (NIC) alongwith an Application
Programming Interface i.e. C-DAC's Virtual Interface Provider
Library (C-VIPL). The non-blocking architecture of the
switch allows multilevel switching for realizing a large
cluster. The switch offers very low latency of the order
of 0.5 µsec. Use of an Interval routing scheme and
group adaptive routing based on Least Recently Used (LRU)
algorithm, ensures uniform bandwidth distribution. The
NIC is based on C-DAC's Communication Co-Processor-III
(CCP-III) chip based on 0.15 micron 1 million gate technology.
Implementation of packetisation & reassembly, flow
control, protection mechanism, address translation and
error recovery in CCP-III, results in low latencies and
very low overheads for the CPU.
PARAM Padma has 12 PARAMNet-II
switches connected in two level configurations to form
a 64-node CLOS network.
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