Any Engineering /Science graduate with mathematics up to 10+2 level.
Sound knowledge of Computing Fundamentals and Basic electronics.
The objective of this course is to provide the student with an expertise in verilog programming as a VLSI design engineer.
|
Sr No
|
Modules
|
Hours
|
|
1
|
Linux Shell Scripting
|
20
|
|
2
|
Advanced Digital Design
|
30
|
|
3
|
HDLs: Verilog
|
72
|
|
4
|
HDLs: Synthesis-II
|
50
|
|
5
|
System Architecture-II
|
48
|
|
6
|
Effective Communications and Soft Skills
|
60
|
|
7
|
Project
|
40
|
|
|
Total
|
320
|
