The High-Performance Image Processing Engine (IPE) is a synthesizable soft IP core designed to offload compute-intensive pixel-level pre-processing and post-processing workloads from the host CPU. Operating as a high-bandwidth memory-to-memory (M2M) hardware accelerator, the IPE core establishes an efficient data-routing bridge between system DDR memory and dedicated computer vision pipelines.

Architecturally, the engine incorporates custom bit-alignment gearboxes that unpack a 128-bit AXI4-Full stream into a continuous 24-bit RGB pixel stream, effectively resolving the hardware challenges associated with non-integer pixel packing. The processing core performs spatial and color-space operations—including weighted grayscale conversion and bilinear resizing—before repacking the processed stream back into a 128-bit structure. The resizing engine utilizes standard Q16.14 fixed-point arithmetic for coordinate scaling, complemented by an interleaved, three-bank Simple Dual-Port Block RAM (BRAM) line-buffer architecture that enables multi-pixel neighborhood reads in a single clock cycle.

For system memory interaction, the core implements independent Read and Write DMA controllers that enforce strict 4096-byte burst alignments. To handle non-standard image resolutions, the hardware dynamically manages padding and data-discarding at the AXI boundaries. This ensures seamless bus transactions and prevents memory alignment faults.

The IP is fully silicon-proven, having been successfully integrated and validated on AMD Xilinx Zynq UltraScale+ MPSoC (ZCU104) and Versal ACAP (VCK190) evaluation boards, where it leverages the programmable Network-on-Chip (NoC) for memory routing at an operating frequency of 150 MHz. System integration is supported via bare-metal C/C++ drivers that handle cache coherency, as well as standalone Board Support Packages (BSP). For OS-based environments, Platform Asset Container (PAC) and PetaLinux support are provided, enabling rapid deployment in custom Linux kernel-space driver layers (Ubuntu-ready) for real-time edge-computing and embedded vision systems.

• Deep Learning Pre-processing: Offloads high-latency image resizing, normalization, and format conversion tasks from host CPUs to accelerate neural network inference pipelines.
• Embedded Vision Systems: Real-time video format conversion and geometric transformations in resource-constrained edge devices, cameras, and robotic vision controllers.
• High-Resolution Video Buffering: Real-time color-space mapping (RGB/YUV/Grayscale) for high-definition and ultra-high-definition display pipelines.
• SoC Acceleration Frameworks: Integrates directly into larger heterogeneous System-on-Chip (SoC) architectures as a plug-and-play streaming pixel processor.

• Hardware-Level Data Gearboxing: Transparently translates between 128-bit system buses and 24-bit internal execution pipelines, preventing pixel-alignment data loss.
• Strict AXI4-Full Compliance: Enforces robust 4096-byte memory burst structures with automated zero-padding and data-discarding logic.
• Highly Synthesizable Design: Written entirely in standard Verilog, allowing target synthesis tools to naturally infer Block RAM (BRAM) and DSP resources without vendor-specific IP lock-in.
• Dual-Domain Synchronization: Features clear separation between the high-speed memory bus clock domain and the processing domain for optimal timing closure.
• Robust Host Handshaking: Supports both high-efficiency polling and interrupt-driven completion flows, enabling smooth integration with host drivers.

• Maximum Resolution: Dynamically configurable via registers up to 4096 × 4096 (4K UHD).
• Operating Frequency: Fully closed timing up to 150 MHz on standard FPGA fabrics.
• Throughput Rate: Processes 1 pixel per clock cycle, delivering a peak throughput of 150 Megapixels per second (MP/s).
• Memory Footprint: Highly resource-efficient, utilizing an interleaved (Even/Odd) Simple Dual-Port BRAM line-buffer architecture to fetch pixel neighborhoods in a single cycle.
• Fixed-Point Precision: Uses standard Q16.14 fixed-point arithmetic for coordinate generation and spatial calculations, preventing the overhead of hardware floating-point units.
• Verification Parity: Validated using a bit-accurate C-reference model and verified through comprehensive system-level AXI VIP testbenches in Vivado.

• FPGA/SoC Target: Synthesizable on any standard FPGA fabric. Verified and implemented on AMD Xilinx Zynq UltraScale+ MPSoC (ZCU104) and Versal ACAP (VCK190) evaluation boards.
• System Requirements: Requires 1x AXI4-Lite Slave interface (Control) and 2x AXI4-Full Master interfaces (Memory Read/Write).
• Software Stack Compatibility: Fully compatible with bare-metal C/C++ drivers, standalone Board Support Packages (BSP), PetaLinux platform assets, and custom Linux kernel-space drivers (Ubuntu-ready).

Abhishek Tiwari, Scientist F

Embedded Systems Group,

C-DAC, Noida

Email: abhishek[at]cdac[dot]in