The Re-configurable Data-flow and Scalable Deep Learning Accelerator (RDFS_DLA) is a sovereign, high-performance computing solution designed to scale seamlessly from low-power edge IoT devices to high-end data center nodes. Built on a robust hardware-software co-design paradigm, the platform addresses the crucial national requirement for energy-efficient, localized, and independent AI acceleration, reducing reliance on proprietary external GPU ecosystems and tool chains.

On the hardware side, the architecture is driven by the unified "FlexiCore" compute engine. FlexiCore unifies matrix, convolutional, pooling, and transformer operations into a single reconfigurable processing cluster. The hardware path is complemented by a template-based design-time RTL generator that enables automatic synthesis of custom architectures based on user-defined constraints. System designers can rapidly generate synthesizable RTL tailored for specific power, performance, and area (PPA) profiles, spanning configurations from 32 to 16,384 MAC units. Additionally, the execution path supports dynamic precision scaling (INT4/INT8) and native structured sparsity, allowing the core to dynamically adapt its data paths at runtime to maximize processing efficiency.

On the software side, the ecosystem provides a robust, compiler-guided execution flow. Pre-trained models from PyTorch, TensorFlow, and TensorFlow Lite are ingested via the standard open ONNX format. The model compiler works in tandem with a cycle-accurate Dataflow Modeler to predict execution latency, manage internal SRAM allocation, and sequence instructions to minimize external DRAM access. The companion NN Optimizer handles advanced network transformations like model pruning, quantization, and operator fusing. At the execution level, standard Linux kernel-mode and user-space drivers ensure stable application deployment on embedded platforms or high-performance PCI boards.

Through this robust integration of reconfigurable hardware and a hardware-aware compiler stack, RDFS_DLA delivers up to 10 TOPS (INT8) and 20 TOPS (INT4) at 1 GHz on a standard 1024 MAC implementation. The platform's complete validation on FPGA prototypes and synthesis compatibility with the TSMC 16nm FFC PDK makes it an integration-ready building block for modern sovereign AI coprocessors, smart cameras, and custom System-on-Chips (SoCs).

• On-Device Edge Surveillance & Smart Cities: Low-latency, on-premise execution of object detection and classification models directly on edge cameras and traffic nodes.
• Offline Medical Diagnostics: Portable diagnostic imaging devices (e.g., portable X-ray or ultrasound tools) running real-time image analysis in remote locations without internet dependency.
• Smart Farming & Precision Agriculture: Low-power embedded vision systems deployed on field sensors or drones for automated crop health monitoring, pest detection, and soil analysis.
• Indigenous HPC Infrastructure: Offloading heavy inference workloads in national supercomputing clusters, serving as a reliable sovereign alternative to imported GPU accelerators.
• Academic & Startup Hardware R&D: A modular, customizable silicon IP block enabling researchers and startups to test custom SoC configurations and explore novel dataflow strategies.

• Unified FlexiCore Architecture: A single, reconfigurable compute cluster that handles convolutions, matrix multiplications, pooling, and transformer operations natively, removing the need for redundant dedicated modules.
• Design-Time & Runtime Reconfigurability: Provides a Python-driven RTL generator for design-time scaling, paired with a runtime-switchable dataflow engine that dynamically selects weight, input, or output-stationary modes based on the active model layer.
• Multi-Precision & Sparsity Support: Native execution of INT4 and INT8 precision alongside hardware-level support for structured sparsity to maximize throughput and minimize memory footprint.
• Co-Designed Software Stack: A mature model ingestion pipeline featuring an NN Optimizer (quantization, pruning, calibration), a Dataflow Modeler to predict cycle latency, and standard Linux/bare-metal drivers.
• Silicon-Ready & Silicon-Agnostic Design: Validated extensively on FPGA prototypes and fully mapped to a TSMC 16nm FFC physical design flow, ensuring rapid integration into broader custom SoCs (such as RISC-V or ARM configurations).

• Compute Precision: Run-time selectable INT4 and INT8.
• Performance Throughput: Peak performance of up to 10 TOPS (INT8) and 20 TOPS (INT4) for a 1024 MAC setup at 1 GHz.
• Inference Speed (ResNet-50): Delivers up to 168 FPS (INT8) and ~336 FPS (INT4) on a 1024 MAC cluster at 1 GHz (measured on cycle-accurate C-model simulations without enabling sparsity).
• Supported Frameworks & Formats: TensorFlow, PyTorch, and TensorFlow Lite via automated ONNX model conversion.
• Supported Neural Networks: CNNs (e.g., ResNet-50, YOLOv3/v4-tiny, VGG16), LSTMs, Transformers, and emerging Small Language Models (SLMs).
• System Interfaces & Memory: AMBA APB-based register interface, AXI-4 memory mapped data bus (supporting 32/64/128-bit widths), smart double-buffered DMA engine, and a configurable 64KB–512KB Flexi-Buffer (CBUF).
• Silicon Target Node: Silicon backend synthesized for TSMC 16nm FFC PDK.

• FPGA Prototyping and Validation: Xilinx Zynq UltraScale+ MPSoC development boards (such as ZCU104 or ZCU106) for hardware-in-the-loop validation and live pipeline demos.
• ASIC Integration: TSMC 16nm FFC PDK (fully compatible with Cadence/Synopsys implementation and verification flows). Can be packaged as a standalone GDSII-compatible IP block or integrated into custom SoCs alongside processors like RISC-V (VEGA/SHAKTI) or ARM.
• Host System OS: Embedded Linux runtime environment or bare-metal setups.

Abhishek Tiwari, Scientist F

Embedded Systems Group,

C-DAC, Noida

Email: abhishek[at]cdac[dot]in