VEGA AT1051 features a 32-bit CPU IP core based on RISC-V Instruction Set Architecture. It is capable of delivering high performance with support for single precision floating point instructions, and MMU for Linux based applications. AT1051 with a 5-stage pipeline comes with branch prediction for efficient branch execution, and Instruction and Data caches. Features include PLIC and vectored interrupts for serving various types of system events. An AXI or AHB standard interface enables ease of system integration.

Targeted for a wide variety of applications which includes High-performance embedded, Consumer Electronics, Motor Control, Industrial Automation, Storage

·        RISC-V IMAFC (RV32IMAFC) Instruction Set Architecture

·        5 stage in-order pipeline implementation

·        16/32-bit mix instruction format for better code density

·        Branch predictor: BTB, BHT, RAS

·        Memory Management Unit (MMU)

·        Harvard architecture (separate instruction and data buses)

·        Supports user, supervisor and machine mode privilege levels.

·        High-performance multiply/divide unit

·        Configurable AXI4 or AHB external interface

·        Configurable, L1 caches

·        8 KiB L1 I-cache (Typical)

·        8 KiB L1 D-cache (Typical)

·        Platform Level Interrupt Controller

·        Up to 127 IRQs

·        Low interrupt latency

·        Vectored interrupt support

·        Linux compatible

·        Zephyr compatible

·        FreeRTOS port

Group Head,

Hardware Design Group,

C-DAC Thiruvananthapuram

Phone: +91-471-2723333 Ext 3243

Email:hdg@cdac.in,tpc@cdac.in