The Reconfigurable Dataflow and Scalable Deep Learning Accelerator (RDFS_DLA) is an indigenous AI accelerator IP and chip development project aimed at enabling high-performance, power-efficient artificial intelligence processing for Edge Computing, High-Performance Computing (HPC), Automotive, Surveillance, Medical Imaging, Smart Camera, and Industrial AI applications. The project focuses on developing a state-of-the-art reconfigurable hardware architecture that can efficiently execute modern deep learning workloads while providing flexibility to adapt to evolving neural network models.

RDFS_DLA features a scalable and reconfigurable architecture that can be configured from 64 to more than 1024 MAC units, enabling deployment across a wide range of applications, from low-power embedded devices to high-performance accelerator platforms. The accelerator incorporates a Flexi Core architecture that combines convolution, pooling, reshape, and matrix operations, along with a Smart DMA engine for efficient memory management and data movement. The design supports INT4 and INT8 precision formats and incorporates dynamic tiling, configurable dataflow, and sparsity-aware processing to maximize performance and resource utilization.

The project delivers a complete ecosystem consisting of FPGA-ready and ASIC-ready RTL, compiler and runtime software, Linux drivers, configuration utilities, dataflow modeling tools, verification environments, and user documentation. The software stack supports popular AI frameworks such as TensorFlow, PyTorch, and TensorFlow Lite, enabling seamless deployment of convolutional neural networks (CNNs), transformers, image classification models, object detection networks, and other AI workloads.

RDFS_DLA supports multiple deployment models, including custom SoC ASICs integrated with ARM or RISC-V processors, System-on-Module (SoM) platforms, and PCIe-based accelerator cards. The architecture is designed to provide design-time and run-time reconfigurability, allowing users to optimize performance, power, area, and memory utilization according to application requirements.

The project contributes towards strengthening India’s semiconductor and AI ecosystem by creating indigenous, reusable, and scalable AI accelerator technology that can accelerate the development of next-generation intelligent systems for both commercial and strategic applications.

1. Smart camera object detection
2. Drone image classification
3. Surveillance video analytics
4. Medical imaging diagnostics
5. Autonomous vehicle obstacle detection

• Scalable from 64 to 1024+ MAC units
• Reconfigurable dataflow architecture
• Flexi Core with integrated pooling and reshape operations
• Smart DMA for efficient memory transfers
• Support for TensorFlow, PyTorch and TFLite
• FPGA-ready and ASIC-ready deliverables
• Dynamic tiling and sparsity support
• Runtime and design-time configurability

• Clock Frequency: up to 1 GHz
• Operating Voltage: 0.8V / 1.8V
• Precision: INT4, INT8
• Internal SRAM: 1 MB to 16 MB
• External Memory Interface: 64/128-bit
• Technology Target: 16nm FFC ASIC-ready assets
• TOPS: Up to 10 TOPS (INT8), 20 TOPS (INT4)

• Hardware: FPGA platforms (ZCU104 and similar high-resource FPGA boards), ARM/RISC-V based system
• based systems
• OS: Linux/Baremetal
• EDA Tools: Synopsys and Cadence tool flows

Abhishek Tiwari, Scientist F

Embedded Systems Group,

C-DAC, Noida

Email: abhishek[at]cdac[dot]in