Any Engineering /Science graduate with mathematics up to 10+2 level.
Sound knowledge of Computing Fundamentals and Basic electronics.
The objective of this course is to provide the student with an expertise in System Verilog programming who wants to make carrier as a VLSI engineer.
|
Sr No
|
Modules
|
Hours
|
|
1
|
OOPs concepts and shell scripting
|
48
|
|
2
|
Advanced Digital Design
|
30
|
|
3
|
Verification with System Verilog
|
142
|
|
4
|
Effective Communications and Soft Skills
|
60
|
|
5
|
Project
|
40
|
|
|
Total
|
320
|
