Workshop Details
Co-located with HiPC 2025, this half day workshop is running in Hyderabad, Telangana, India and will be on Wednesday 17th December 2025.
Important dates
| Submission site open (latest by) | September 1, 2025 |
| Full Paper submissions (latest by) | October 03, 2025 (AoE) |
| Author notifications (latest by) | November 6, 2025 |
| Camera-ready version (firm deadline) | November 14, 2025 |
| Workshop | Wednesday 17th December 2025 |
Workshop scope
RISC-V is an open, modular, and extensible Instruction Set Architecture (ISA) that is rapidly gaining global attention for its potential to foster innovation across computing domains. Its royalty-free nature and open governance model encourage collaboration among academia, industry, and research institutions. While RISC-V has already seen significant success in embedded systems, IoT devices, and edge computing, its possibilities for High-Performance Computing (HPC) are only starting to emerge.
HPC continues to drive breakthroughs in science, engineering, and data analytics by enabling complex simulations, large-scale computations, and machine learning workloads. The growing need for energy-efficient, customizable, and high-performance solutions makes RISC-V an attractive option. Recent developments such as the standardization of vector extensions, advancements in cache coherence mechanisms, and the evolution of high-speed interconnects have enhanced RISC-V’s readiness for demanding HPC applications. These innovations present new opportunities to design processors and systems that meet the diverse needs of supercomputing.
This workshop aims to provide a platform for researchers, hardware designers, system software developers, toolchain maintainers, application scientists, and integrators to exchange ideas on the role of RISC-V in HPC. The event will feature discussions on experiences from early deployments, performance evaluations, architectural innovations, and software ecosystem enhancements. We particularly welcome participation from academic institutions, industry experts, government research labs, and non-profits across India, Asia, and the global HPC community.
By focusing on both the challenges and the potential of RISC-V for HPC, this workshop seeks to build connections among stakeholders and promote open hardware in supercomputing. Our goal is to inspire future architectures and solutions that are open, flexible, and driven by community collaboration, complementing HiPC’s mission to advance state-of-the-art HPC research.
Call for papers - workshop topics
We invite submissions of high-quality, original research results and works-in-progress on RISC-V with a general connection to HPC. Topics of interest for this workshop include (but are not limited to):
- Architectural features and innovations of RISC-V for HPC workloads.
- Compiler, runtime, and toolchain development for RISC-V HPC systems.
- Experiences and challenges in porting HPC applications to RISC-V.
- Benchmarking and performance evaluation of RISC-V-based HPC platforms.
- System software, including OS, virtualization, and resource management for RISC-V clusters.
- Co-design approaches involving RISC-V CPUs, accelerators, and interconnects.
- Integration of RISC-V in heterogeneous and exascale HPC architectures.
- Opportunities for customization and specialization of RISC-V for domain-specific HPC workloads.
- Security, reliability, and resilience considerations in RISC-V-based HPC systems.
- Experiences from prototype deployments and testbeds involving RISC-V for HPC.
- Roadmaps, open challenges, and community efforts for advancing RISC-V in HPC.
- Efforts in standardization, ecosystem building, and community-driven development for RISC-V HPC.
We welcome
- Short paper: 4 pages (including references, figures, tables)
- Full Paper: minimum 6 and up to 8 pages (including references, figures, tables)
Paper submission
Submissions must be in PDF format and follow the IEEE 2-column conference style (10-pt font on 8.5"×11" pages). The official IEEE conference templates are available here: https://www.ieee.org/conferences/publishing/templates.html. Page limits include all contentfigures, tables, references, and appendices unless specified otherwise.
All papers should present original, unpublished work and must not be under review elsewhere. A single-blind peer review process will be used for evaluation. Accepted papers will be presented at the workshop and included in the companion proceedings of HiPC, accessible via IEEE Xplore.
At least one author of each accepted paper must register for HiPC 2025 and present the work at the workshop to ensure inclusion in the official proceedings.
Submission link : https://easychair.org/conferences?conf=riscvhpc2025
Organisation
Organising committee
- Sanjay Wandhekar, C-DAC, India
- Ashish Kuvelkar, C-DAC, India
- Yogeshwar Sonawane, C-DAC, India
- Surendra Billa, C-DAC, India
- Nick Brown, EPCC at the University of Edinburgh, UK
- Teresa Cervero, Barcelona Supercomputing Center (BSC), Spain
Program committee
- Nick Brown, EPCC, University of Edinburgh, UK
- Teresa Cervero, BSC, Spain,
- Filippo Mantovani, BSC, Spain
- Neel Gala, Incoresemi, India
- Daniele Gregori, E4 - Italy
- Prof. Sujay Deb, IIIT, Delhi
- Xavier Martorell, BSC, Spain
- Manolis Marazakis, FORTH, Greece
- Sanjay Wandhekar, C-DAC, India
- Ashish Kuvelkar, C-DAC, India
- Atul Bodas, C-DAC, India
- Libin T T, C-DAC, India
- Olivier Sentieys, INRIA, France
For all queries, please contact:riscvhpc2025[at]cdac[dot]in